Several basic device architectures exist in the art for constructing image sensor arrays. Two of these are the frame transfer and line-address architectures. These architectures generally have a plurality of CCD elements arranged in rows and columns. For each CCD photosite well, an additional well separated by a barrier needs to be fabricated adjacent to it for receiving the stored charge. Further, pixel density is decreased by the requirement of channel stops. In certain of these devices, drains are formed in the channel stops to prevent blooming, and this occupies further array area.
Another class of imagers is arranged according to the interline transfer architecture. These devices comprise a plurality of photosites that can be either empty CCD wells or photodiodes. The photosites are separated by columns of CCD elements provided for readout of the signal. The necessity for the CCD columns decreases pixel density. Channel stops and barriers are required since CCD elements are used in the structure, and this further decreases pixel density.
Yet another class of devices uses an X-Y architecture, wherein each cell or element is individually addressed in the X and Y direction in order to read it out. Conventional X-Y architectures include charge injection devices (CIDs), MOS transistor devices and, more recently, charge-modulated transistor devices. In the CID device, two gates are formed, one connected to a column line, and another connected to a row line. CID arrays have long readout leads, and therefore, have a large parasitic capacitance. This in turn lowers the dynamic range of the device because of the kTC noise associated with the long, high-capacitance readout lines. Further, since each cell is required to be separately read out, the readout of an entire row of cells takes a considerable time. The high-density television (HDTV) format requires that the addressing and readout of an image sensor array used in connection therewith be done within a standard 53.5-microsecond period. Thus, if there are 1000 elements in a row of a CID array device that is operated in the HDTV format, each element in the row must be addressed and read out in 53.5 nanoseconds. This is very difficult to accomplish because of the RC time constant associated with charging up the readout lines, which in turn limits the size of CID image sensor arrays. Further, the relatively large time necessary to read out the row of elements increases smear.
MOS transistor arrays have the same problems as CID arrays relative to their long, large-capacitance sense lines. In addition, the charge from each address element is not amplified, but is instead read out directly on these sense lines. Pixel density of these device arrays is reduced by the requirement of forming either one or two transistors at each photosite for addressing purposes. The kTC noise associated with the long and large-capacitance sensing lines of these X-Y architectures usually degrades the device performance below that of other comparable CCD devices. This noise is a statistical uncertainty in the amount of charge stored on a capacitive element, and equals the square root of the Boltzmann constant (k), multiplied by the absolute temperature (T) and the capacitance of the sense line (C).
Recently, a charge-modulated MOS transistor image sensor element has been devised that can operate in a non-destructive readout mode. This device is described in Matsumoto, K., T. Nakamura, et al., "A New MOS Phototransistor Operating in a Non-Destructive Readout Mode,"Japanese Journal of Applied Physics, Vol. 24 No. 5, Pages L323-L325 (May, 1985). This element comprises an MOS phototransistor that has an N channel formed in its semiconductor gate region in the bulk. When the gate of the MOS transistor is illuminated, photogenerated holes are stored in the depletion layer under the gate. The stored holes increase the surface potential, resulting in reduction of the potential barrier height at the saddle point for the N-channel carriers. As a result, an amplified current modulated by the surface potential flows in the N bulk channel from source to drain, showing triode-like current-voltage characteristics.
While this MOS phototransistor device has the potential for non-destructive readout, it still has the problem of kTC noise, as the holes stored next the surface of the semiconductor layer will not be entirely swept out by a reset pulse applied to the gate due to the traps existing at the silicon-silicon dioxide interface. The device also suffers from pattern noise since it is designed to modulate the current as will be explained below.
Further, the X-Y architecture of this device is not suitable for use in high-density television (HDTV) applications for reasons discussed in relation to CID elements above. The long readout time exacerbates such problems as smearing, and element to-element charge leakage from unaddressed rows.
The above-mentioned transistor sensing elements have a further disadvantage in that they produce a modulated current as an output signal. This current signal will vary both in relation to the size of the sensing element producing the signal and its threshold voltage. Variations in size and threshold voltage therefore produce "pattern noise." The threshold and size parameters of the sensing elements must therefore be tightly controlled; however, this control becomes progressively more difficult as the size of the element decreases.
A need therefore exists in the industry for a sensor element that has negligible pattern and kTC noise, can be integrated into each photosite, has a high charge-to-voltage conversion sensitivity, has a large charge storage capacity, has resistance to pattern noise, has good blooming overload protection, has a high pixel-to-pixel uniformity and can be arranged for a sufficiently fast readout for use in HDTV applications.